The Intel Xeon Phi Users Group (IXPUG) will be holding its 2016 Annual Meeting this year at Argonne National Laboratory, 19-23 September 2016. The Call for Presentations is open until 18 August 2016. Even if you don’t plan to attend, you may be interested inÂ joining IXPUG.
We are pleased to announce that the Call for Proposals for the Aurora Early Science Program is now open. The deadline for submission is Sept. 2, 2016. Feel free to share this information with those you think might be interested in submitting a proposal.
Those of you on Theta ESP project teams should have received an email yesterday with a link to the registration page for the August hands-on workshop. Please do not share it beyond your project team; attendance is only open to ESP project team membersâspecifically the right people to make progress running, scaling, and benchmarking the project applications on Theta.
There are now links to KNL presentations given at this week’s IXPUG WorkshopÂ at the ISC16 conference. (IXPUG = Intel Xeon Phi Users Group)
We now have two more KNL white box nodes available to ESP users, for a total of three. You were directly emailed with access instructions a while back. If you lost those instructions or otherwise have questions about access, email firstname.lastname@example.org
We anticipate the arrival of 8 single-node KNL systems in May.Â Those systems will be made available to all ESP project team members, with no requirement that your home institution has signed the MP-NDA agreement with Intel. Email will go out to everyone when the systems are available, with instructions for access and usage.
You may find this website useful for finding and discussing information about the Intel KNL chip:
NERSC is offering an Advanced OpenMP training day this Thursday. Itâs still possible to sign up to attend virtually (Zoom), if youâre interested. If you don’t have a NERSC login id, indicate on the registration form that you heard about the training via the ALCF Early Science Program:
Dear NERSC users,
We are pleased to announce a one-day training on “Advanced OpenMPâ:
Speakers: Michael Klemm, Intel (OpenMP Language Committee Member),
Â Â Bronis R. de Supinski, LLNL (Chair of the OpenMP Language Committee)
Time: Thursday, February 4, 9am – 5pm PST
Location: NERSC/LBNL (attend in person or remote)
The OpenMP 4.5 specification was released in November 2015. This tutorial will quickly review the basics of OpenMP programming, with the assumption that attendees understand basic parallelization concepts. Next, the tutorial will detail performance tuning aspects, such as memory placement and affinity considerations, and exploitation of vector units. The presenters will then discuss advanced OpenMP language features in-depth, with an emphasis on tasking, cancellation and new additions in OpenMP 4.5. Using OpenMP from an MPI application and potential pitfalls will also be discussed.
Levels of the tutorial materials are: beginner 10%, intermediate 45%, and advanced 45%. Afternoon hands-on sessions on OpenMP Analysis in VTune and Using SIMD will use the NERSC Cori (Cray XC40 with Intel Haswell processors) and Babbage (Intel Xeon Phi KNC testbed) systems.
Please find more detailed tutorial description, speakers bio, registration, agenda, and in person and remote attendance information at:
In person registration will close on Thursday, January 28.
NERSC User Services
The Theta Early Science Program Confluence space is now available. This is meant to function like a Wiki, but using the Confluence technology. Anyone from Theta ESP projects may put content in the space, and for the most part its structure should evolve organically. ALCF will put content here as well, such as slides and videos from ESP meetings, instructions for accessing early hardware when it becomes available, etc. Do not include any NDA information (Intel or Cray) in content you put in this space; we will have another venue for that if/when needed.
The video recordings of the Kick-Off and Training Session 1 videoconferences are available on the Confluence site: Expand âMeetings/Workshopsâ under the navigation panel at the left and click to bring up the relevant meeting page.
To get access to the site, follow these instructions:
- Sign up for a Confluence account:
- Go to https://collab.cels.anl.gov and in the top-right corner of the webpage, click “Sign upâ.
- On the Sign Up screen, enter your contact information, including yourÂ preferred email address and click the “Sign upâ button.
- Obtain access to the Theta ESP Wiki space:
- Send an email to email@example.com with your Confluence username requesting access to the Theta ESP wiki.
- You will be notified via email within two business days when you have been added to the Theta ESP wiki along with the link to the login.
- Log into the Theta ESP Wiki space:
There will beÂ a training-session videoconference on Wednesday 9 September, from 10:00 AM – 5:30 PM CDT.
The purpose of the meeting is to introduce Theta hardware, particularly the Knights Landing CPU, and the software tools to program it. Presentations will be given by Intel and Cray speakers. See agenda on the meeting website.
The intended audience is ALCF Theta ESP project members who will be working on code development and testing for Theta. You will receive an invitation to participate, either directly or through your project’s PI/co-PI. Session content will include Intel NDA material, so attendeesâ institutions must have an appropriate nondisclosure agreement signed with Intel.
To register for the videoconference, please visit the Videoconference Registration Site.